1 Introduction 1.1 Motivation and Background 1.2 Book Organization2 Sigma-Delta Modulation 2.1 Introduction 2.2 First Order Sigma-Delta Modulator 2.3 Second Order Sigma-Delta Modulator 2.4 Higher Order Sigma-Delta Modulator 2.4.1 The MASH Structure3 Architecture and High Level Model 3.1 Passive Integrator 3.1.1 Ultra Incomplete Settling 3.1.2 Discrete Time Transfer Function of the SC Integrator 3.1.3 Thermal Noise Analysis 3.2 Modulator Block Diagram 3.2.1 Signal and Noise Transfer Functions 3.3 Proposed Architecture 3.4 High Level Model 3.5 Optimization 3.6 Reducing the Size of the Capacitors4 Electrical Circuits and Simulation Results 4.1 Introduction 4.2 Digital Circuitry 4.2.1 Logic Gates 4.2.2 Delay Circuits 4.2.3 Phase Generator 4.2.4 Flip-Flop 4.3 Amplifiers 4.3.1 Gain G2 4.3.2 Gain Gmid 4.4 Comparator 4.5 Switching Circuitry 4.5.1 Clock Bootstrapped Switch 4.6 Feedback and Reference Voltages 4.7 Monostable Circuit 4.8 Simulation Results 4.8.1 Second Order ΣΔ Modulator 4.8.2 Third Order MASH ΣΔ Modulator 4.8.3 Third Order MASH ΣΔM with Monostable Circuit5 Conclusions 5.1 Final RemarksReferences