Driven by applications such as telecommunications, computing and consumer/multimedia and facilitated by the progress in CMOS ULSI technology, the microelectronics IC market is characterized by an ever-increasing level of integration complexity. Complete systems, that previously occupied one or more boards, are integrated on a few chips or even on one single multi-million transistor chip - a so called System-on-Chip (SoC). Although most functions in such integrated systems are implemented with digital or digital signal processing circuitry, the analogue circuits needed at the interface between the electronic system and the continuous-valued outside world are also being integrated on the same die for reasons of cost and performance. Unfortunately, the integration of both analogue and RF circuits and digital circuits on the same die not only offers many benefits, but also creates some technical difficulties. Since the analogue circuits exploit the low-level physics of the fabrication process, they remain difficult and costly to design, but they are also vulnerable to any kind of noise or crosstalk signals.
The higher levels of integration (moving towards 100 million transistors per chip clocked at ever higher frequencies) make the mixed-signal signal integrity problem increasingly challenging. One of the most important problems is the parasitic supply and substrate noise coupling, caused by the fast switching of the digital circuitry that then propagates to the sensitive analogue circuitry via the common substrate. It is therefore important to be able to predict the impact of digital switching noise on the analogue circuit performance at the design stage of the integrated system, before the chip is taped out for fabrication, and to understand how this problem can be reduced. This text provides an overview of state-of-the-art research results in the field of substrate noise analysis and reduction techniques. Much of the reported work has been established as part of the Mixed-Signal Initiative of the European Union.